This invention relates to electronic circuits and, more particularly, to circuits which implement Boolean functions.
Many software and hardware applications require the implementation of Boolean functions such as AND, OR, NAND, NOR, EXCLUSIVE-OR, etc. Most Boolean functions may be implemented by interconnecting a plurality of transistors in such a way that binary signals representing input values are applied to control terminals of the transistors and the result of the logical expression is output from a node somewhere within the circuit. The circuits are often classified as static or dynamic. For example, FIG. 1 is a schematic diagram of a known static circuit 10 for implementing a NOR function (A+B). Circuit 10 comprises PMOS transistors 14, 18 and NMOS transistors 22, 26. The binary signal representing the A value is applied to a gate terminal 30 of PMOS transistor 14 and to a gate terminal 34 of NMOS transistor 26. The binary signal representing the B value is applied to a gate terminal 34 of PMOS transistor 18 and to a gate terminal 38 of NMOS transistor 22. A source terminal 42 of PMOS transistor 14 is coupled to a V.sub.DD potential, and a drain terminal 46 of PMOS transistor 14 is coupled to a source terminal 50 of PMOS transistor 18 at a node 54. A drain terminal 58 of PMOS transistor 18 is coupled to an (A+B) output line 62 at a node 64. Drain terminals 68, 72 of NMOS transistors 22, 26 respectively are coupled to (A+B) output line 62 at respective nodes 76 and 78. Source terminals 82, 84 of NMOS transistors 22 and 26 are coupled to a ground potential. From inspection of circuit 10, it should be readily apparent that when both A and B are low, then transistors 14 and 18 conduct current into node 64. At this time transistors 22 and 26 are nonconducting. Thus, output line 62 is pulled high. On the other hand, if either A or B are high, then the respective PMOS transistor 14 or 18 is rendered nonconducting. Simultaneously, one or both of NMOS transistors 22 or 26 conducts current away from node 64, and output line 62 is pulled low.
One problem with circuit 10 is that, since PMOS transistors are not as conductive as NMOS transistors for a given size, PMOS transistors 14 and 18 typically must have a considerably larger size than transistors 22 and 26. Not only does this consume valuable chip area, but the logic elements which generate the A and B signals must therefore drive more input capacitance. Another problem, shared by all static circuits of this type (and those described below), is that half the circuit becomes nonconducting at any transition (e.g., when A and B go high, PMOS transistors 14, 18 are off and NMOS transistors 22, 26 are on). The nonconducting transistors act as an unnecessary load to the inputs as well as the outputs. Furthermore, the series connection of PMOS transistors 14 and 18 creates unwanted delay through the circuit. Since there must be a series connected PMOS transistor for every input signal, the complexity and delay of the circuit becomes unacceptable very quickly as the number of inputs increase. The same would be true for a NAND circuit although in that case delay and complexity would be caused by serially connected NMOS transistors.
FIG. 2 is a schematic diagram of a circuit 100 which attempts to overcome the problems of circuit 10 shown in FIG. 1. Circuit 100 comprises PMOS transistors 104, 108 and NMOS transistors 120, 122, 124 and 126. The A input signal is applied to a gate terminal 128 of NMOS transistor 120, and the B input signal is applied to a gate terminal 130 of NMOS transistor 122. The complement of the A input signal is applied to a gate terminal 132 of NMOS transistor 124, and the complement of the B input signal is applied to a gate terminal 34 of NMOS transistor 126. A source terminal 138 of PMOS transistor 104 is coupled to V.sub.DD, and a drain terminal 140 of PMOS transistor 104 is coupled to an (A+B) output line 144 at a node 142. A source terminal 146 of PMOS transistor 108 is also coupled to V.sub.DD, and a drain terminal 148 of PMOS transistor 108 is coupled to an (A+B) output line 152 at a node 150. A gate terminal 154 of PMOS transistor 104 is coupled to node 150, and a gate terminal 158 of PMOS transistor 108 is coupled to node 142.
Drain terminals 160, 162 of NMOS transistors 120 and 122, respectively, are coupled to (A+B) output line 144 at respective nodes 164 and 142. Source terminals 168, 170 of NMOS transistors 120 and 122 are coupled to a ground potential. A drain terminal 172 of NMOS transistor 124 is coupled to node 150, and a source terminal 174 of NMOS transistor 124 is coupled to a drain terminal 176 of NMOS transistor 126 at a node 180. A source terminal 184 of NMOS transistor 126 is coupled to a ground potential.
When either A or B are high, then one or both of NMOS transistors 120 or 122 conduct current away from their respective nodes 164 or 142, which tends to pull (A+B) output line 144 low. Additionally, one or more of NMOS transistors 124 or 126 are rendered nonconducting and prevent current flow away from node 150. As node 142 is pulled low, PMOS transistor 108 begins conducting current into node 150, thus pulling (A+B) output line 152 high. The high signal at node 150 renders transistor 104 nonconducting, and the circuit reaches a final state where (A+B) output line 144 is low and (A+B) output line 152 is high. If both A and B are low, then NMOS transistors 120 and 122 are both rendered nonconducting and NMOS transistors 124 and 126 conduct current away from node 152. The result is then a high signal at (A+B) output line 144 and a low signal at (A+B) output line 152.
While circuit 100 eliminates the serially connected stack of PMOS transistors shown in circuit 10 of FIG. 1, it is not without its own disadvantages. For example, circuit 100 requires both the A and B signals and their complements as inputs, thus requiring an inverter stage between NMOS transistors 120, 122 and NMOS transistors 124, 126. This, in turn, adds delay to the circuit and doubles interconnect routing as the inverted signals are fed to their corresponding inputs. Also, there must be as many serially coupled NMOS transistors coupled to node 150 as there are inputs, thus providing further delay in the circuit operation. Furthermore, circuit 100 relies on NMOS transistors 120, 122 to overcome any current flow from PMOS transistor 104 to pull (A+B) output line 144 low and change the existing state of the circuit when PMOS transistor 104 is conducting and PMOS transistor 146 is nonconducting. Similarly, NMOS transistors 124 and 126 must overcome any current flow from PMOS transistor 108 to pull (A+B) output line 152 low and change the existing state of the circuit when PMOS transistor 104 is nonconducting and PMOS transistor 146 is conducting. The fight between the PMOS transistors attempting to pull up their respective nodes and the NMOS transistors attempting to pull down their respective nodes prevents the circuit from responding quickly to input signal transitions. Thus, on the one hand, one cannot size PMOS transistors 104 and 108 too large or else they may prevent NMOS transistors 120 and 122 or NMOS transistors 124 and 126 from performing their function. On the other hand, PMOS transistors 104 and 108 cannot be sized too small or else any high signal on (A+B) output line 144 or (A+B) output line 152 will take too long to generate.
FIG. 3 is a schematic diagram of a circuit 200 which attempts to overcome some of the problems of circuit 100 shown in FIG. 2. Circuit 200 is an improvement of circuit 100, and the components which remain the same are numbered identically. Briefly, circuit 200 is the same as circuit 100 with the addition of NMOS transistors 204, 208, 212 and 216. The complement of the A input signal is applied to a gate terminal 220 of NMOS transistor 204, the complement of the B input signal is applied to a gate terminal 224 of NMOS transistor 208, the A input signal is applied to a gate terminal 228 of NMOS transistor 212, and the B input signal is applied to a gate terminal 232 of NMOS transistor 216 for reasons discussed below. A drain terminal 236 of NMOS transistor 204 is coupled to V.sub.DD, and a source terminal 240 of NMOS transistor 204 is coupled to a drain terminal 242 of NMOS transistor 208 at a node 244. A source terminal 248 of NMOS transistor 208 is coupled to (A+B) output line 144 at a node 250. Drain terminals 254, 256 of NMOS transistors 228, 232, respectively, are coupled to V.sub.DD, and source terminals 258 and 260 of NMOS transistors 212, 216, respectively, are coupled to (A+B) output line 152 at respective nodes 262 and 264.
If A or B is high, then one or both of NMOS transistors 204 or 208 are nonconducting, and (A+B) output line 144 is pulled low by whichever NMOS transistor 120 or 122 is conducting at the time. This tends to turn on PMOS transistor 108. At the same time, one or both of NMOS transistors 124 or 126 are nonconducting while one or both of NMOS transistors 212 or 216 are conducting current into (A+B) output line 152, thus aiding PMOS transistor 108 in pulling (A+B) output line 152 high. On the other hand, if A and B are both low, then NMOS transistors 212, 216 are nonconducting, and (A+B) output line 152 is pulled low by NMOS transistors 124, 126. This tends to turn on PMOS transistor 104. At the same time, NMOS transistors 120, 122 are nonconducting, while NMOS transistors 204, 208 conduct current into (A+B) output line 152, thus aiding PMOS transistor 104 in pulling (A+B) output line 144 high. While the addition of NMOS transistors 204, 208, 212, and 216 may overcome the sizing limitations of PMOS transistors 104 and 108, they do not eliminate the requirement of generating both the original input signal and its complement, and serially connected NMOS transistors (one per input) must still be coupled to node 150. In fact, circuit 200 exacerbates the problem by adding serially connected NMOS transistors 204, 208 to node 250. Furthermore, the added transistors 204, 208, 212 and 216 consume additional chip area.
FIG. 4 is a schematic diagram of a dynamic circuit 300 which attempts to overcome the problems noted in circuits 10, 100 and 200. Circuit 300 comprises a PMOS transistor 304, NMOS transistors 308, 312, 316 and an inverter 320. The A input signal is applied to a gate terminal 324 of NMOS transistor 308, and the B input signal is applied to a gate terminal 328 of NMOS transistor 312. A precharge signal is applied to a gate terminal 332 of PMOS transistor 304 and to a gate terminal 336 of NMOS transistor 316. A source terminal 340 of PMOS transistor 304 is coupled to V.sub.DD, and a drain terminal 344 of PMOS transistor 304 is coupled to an input terminal 348 of inverter 320 at a node 352. An output terminal of inverter 320 functions as an (A+B) output line 356. Drain terminals 360, 364 of NMOS transistors 308, 312, respectively, are coupled to node 352, and source terminals 368, 372 of NMOS transistors 308, 312 are coupled to a drain terminal 376 of NMOS transistor 316 at a node 380. A source terminal 384 of NMOS transistor 316 is coupled to a ground potential.
In operation, a low signal is applied to gate 332 of PMOS transistor 304 and to gate terminal 336 of NMOS transistor 316 during a precharge cycle, thus rendering PMOS transistor 304 conductive while rendering NMOS transistor 316 non-conductive. This, in turn, allows node 352 to be precharged to a high potential regardless of the state of the A and B input signals applied to gate terminals 324, 328 of NMOS transistors 308, 312, respectively. Thereafter, a high signal is applied to gate 332 of PMOS transistor 304 and to gate terminal 336 of NMOS transistor 316 during an evaluate cycle, thus rendering PMOS transistor non-conductive and rendering NMOS transistor conductive. If one or both of the A or B signals are high, then one or both of NMOS transistors 308 or 312 are rendered conductive, thus pulling node 352 low, which results in a high signal on (A+B) output line 356. On the other hand, if both A and B are low, then NMOS transistors 308 and 312 remain non-conductive, node 352 remains at a high potential, and a low signal remains on (A+B) output line 356. While circuit 300 overcomes some of the problems of the previous discussed circuits, such as one set of transistors attempting to overcome the operation of another set of transistors, it too has disadvantages. For example, FIG. 5 shows a series of NMOS transistors 410A, 410B, . . . , 410N, each having their drain terminals 412A, 412B, . . . , 412N coupled to an input terminal 414 of an inverter 416 at respective nodes 418A, 418B, . . . , 418N. Source terminals 420A, 420B, . . . , 420N are coupled to a ground potential or to some other current sink. A precharge circuit 424 is coupled to input terminal 414 at a node 426 for precharging input terminal 414 to a high potential as with input terminal 348 of circuit 300.
As is known in the art, inverter 416 has a capacitance 430 associated with it, and each NMOS transistor 410A, 410B, . . . , 410N has respective capacitances 434A, 434B, . . . , 434N associated with it. When the number of NMOS transistors are small, then capacitance 430 associated with inverter 416 is the primary capacitance in the system and it is easily precharged by precharge circuit 424 and discharged by the NMOS transistors. However, as the number of NMOS transistors become large, the aggregate capacitances associated with the plurality of NMOS transistors becomes so large that it becomes the dominant capacitance and degrades performance to an unacceptable level as individual NMOS transistors attempt to discharge the very large capacitance. The problem cannot be solved by increasing the size of the NMOS transistors, because then the associated capacitances also increase.